A. Field of the Invention
The present invention relates to a random access memory, and more particularly, to a RAM wherein the two pages making up the memory are interweaved to conserve space on a semi-conductor chip.
B. Description of the Prior Art
A RAM includes a plurality of field effect transistors and other circuit elements which are fabricated on a semiconductor chip to form a number of memory cells. The memory cells are normally arranged in a matrix array consisting of rows and columns of cells. (As a matter of convention, the term "row" relates to horizontal arrangements and the term "column" relates to vertical arrangements, but it will be understood that those terms, as here used, may be interchanged or otherwise applied, the terms being here used in their generic senses.) Address circuitry is utilized to select a particular memory cell in the array and data input and output connections are provided so that data can be read from or written into the selected memory cells. Signals from the addressing circuitry and data to and from the individual memory cells are carried on conductors or bit lines which are situated along each of the rows and down each of the columns of the memory.
In most memory configurations, the primary consideration has been to modify the width-to-length ratio of the memory cells to create greater packing density for these cells on a semi-conductor chip. Little attention has been paid to the placement of the peripheral circuitry associated with the RAM. Because of this, wasted space may be present in the chip layout which causes a reduction in both the capacity of the memory and the availability on the chip for the placement of other elements.